#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__

/* RT-Thread Project Configuration */

/* RT-Thread Kernel */

#define RT_NAME_MAX 16
// #define RT_USING_SMP
// #define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
// #define SYSTEM_THREAD_STACK_SIZE 1024
// #define RT_USING_TIMER_SOFT
// #define RT_TIMER_THREAD_PRIO 4
// #define RT_TIMER_THREAD_STACK_SIZE 1024

/* kservice optimization */

#define RT_DEBUG
#define RT_DEBUG_COLOR

/* Inter-Thread communication */

#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
// #define RT_USING_EVENT
#define RT_USING_MAILBOX
// #define RT_USING_MESSAGEQUEUE
// #define RT_USING_SIGNALS

/* Memory Management */  // STM32 RTCONFIG.H

#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
// #define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
// #define RT_USING_MEMTRACE
#define RT_USING_HEAP

/* Kernel Device Object */

#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_INTERRUPT_INFO
// #define RT_USING_CONSOLE
// #define RT_CONSOLEBUF_SIZE 256
// #define RT_CONSOLE_DEVICE_NAME "uart0"

// #define RT_VER_NUM 0x40101
// #define ARCH_ARM
// #define RT_USING_CPU_FFS
// #define ARCH_ARM_CORTEX_A
// #define RT_USING_GIC_V2
// #define ARCH_ARM_CORTEX_A9

/* RT-Thread Components */

#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2024
#define RT_MAIN_THREAD_PRIORITY 10
// #define RT_USING_MSH
// #define RT_USING_FINSH
// #define FINSH_USING_MSH
// #define FINSH_THREAD_NAME "tshell"
// #define FINSH_THREAD_PRIORITY 20
// #define FINSH_THREAD_STACK_SIZE 4096
// #define FINSH_USING_HISTORY
// #define FINSH_HISTORY_LINES 5
// #define FINSH_USING_SYMTAB
// #define FINSH_CMD_SIZE 80
// #define MSH_USING_BUILT_IN_COMMANDS
// #define FINSH_USING_DESCRIPTION
// #define FINSH_ARG_MAX 10
// #define RT_USING_DFS
// #define DFS_USING_POSIX
// #define DFS_USING_WORKDIR
// #define DFS_FILESYSTEMS_MAX 4
// #define DFS_FILESYSTEM_TYPES_MAX 8
// #define DFS_FD_MAX 32
// #define RT_USING_DFS_ELMFAT


/* Device Drivers */

// #define RT_USING_DEVICE_IPC
// #define RT_USING_SYSTEM_WORKQUEUE
// #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
// #define RT_SYSTEM_WORKQUEUE_PRIORITY 23
// #define RT_USING_SERIAL
// #define RT_USING_SERIAL_V1
// #define RT_SERIAL_USING_DMA
// #define RT_SERIAL_RB_BUFSZ 64
// #define RT_USING_I2C
// #define RT_USING_I2C_BITOPS
// #define RT_USING_PIN
// #define RT_USING_MTD_NOR
// #define RT_USING_MTD_NAND
// #define RT_MTD_NAND_DEBUG
// #define RT_USING_RTC
// #define RT_USING_SOFT_RTC
// #define RT_USING_SDIO
// #define RT_SDIO_STACK_SIZE 512
// #define RT_SDIO_THREAD_PRIORITY 15
// #define RT_MMCSD_STACK_SIZE 1024
// #define RT_MMCSD_THREAD_PREORITY 22
// #define RT_MMCSD_MAX_PARTITION 16
// #define RT_USING_SPI
// #define RT_USING_SPI_MSD
// #define RT_USING_SFUD
// #define RT_SFUD_USING_SFDP
// #define RT_SFUD_USING_FLASH_INFO_TABLE
// #define RT_SFUD_SPI_MAX_HZ 50000000
// #define RT_USING_WDT



#endif
